How Are Solar Panels Made? From Sand to Silicon to Module

Every solar panel on a rooftop in Surat, a 100 MW ground-mount in Rajasthan, or a permit set Heaven Designs engineers for a US C&I project started as silica sand—one of the most ordinary materials on Earth. The journey from that sand grain to a finished 580 Wp TOPCon module involves nine discrete manufacturing stages, temperatures exceeding 2,000°C, chemical purification to one-billionth of a percent contamination, and precision diamond-wire slicing that produces wafers thinner than two human hairs. Understanding that journey matters for EPCs not as trivia, but because every step in the manufacturing process corresponds to a quality variable that shows up in your PVsyst yield model, your ALMM compliance check, and your 25-year performance warranty.

Solar panels are manufactured through a nine-stage process starting with the reduction of quartz sand (SiO₂) to metallurgical-grade silicon at 2,000°C, followed by Siemens-process purification to solar-grade (9N) silicon, Czochralski or directional solidification crystal growth, diamond-wire wafer slicing, phosphorus doping to form a p-n junction, anti-reflective coating, metal contact screen printing, cell interconnection, and final lamination into an aluminum-framed glass module. The critical quality fork occurs at the crystal growth stage: monocrystalline (Czochralski) wafers produce 22–24% efficiency cells with uniform grain structure, while multicrystalline (directional solidification) wafers yield 17–19% efficiency cells with visible grain boundaries. India’s ALMM list now covers predominantly monocrystalline TOPCon and PERC modules from domestic manufacturers.

This article follows the Sand-to-System Quality Ladder (SSQL) — Heaven Designs’ proprietary framework mapping each manufacturing stage to the specific quality checkpoint that affects long-term yield, so EPCs and developers can read a module datasheet and a manufacturer’s process documentation as a unified risk document.

Stage 1: Silicon Extraction — Why “Solar-Grade Sand” Is Not Beach Sand

Silicon is the second most abundant element in the Earth’s crust, constituting about 28% by mass. But the silicon in quartz beach sand comes contaminated with iron, aluminum, titanium, calcium, and dozens of trace metals—each of which, at parts-per-million concentrations in a solar cell, acts as a recombination center that kills electron lifetime and destroys efficiency.

The starting material for solar-grade silicon is high-purity quartz rock (SiO₂ content >99.5%), not beach sand. Major deposit regions include Brazil, Norway, and parts of Rajasthan and Karnataka in India. The quartz is crushed, washed, and fed into an electric arc furnace with a carbon reductant (coal, charcoal, or petroleum coke) at approximately 2,000°C.

The carbothermic reduction reaction:

SiO₂ + 2C → Si + 2CO₂

The product is metallurgical-grade silicon (MG-Si) at roughly 98–99% purity—high enough for aluminum alloying and chemical manufacturing, but far too contaminated for solar cells. A single part-per-million of iron in a silicon wafer can reduce solar cell efficiency by 0.5–1%.

Stage 2: Siemens Process — Achieving 9N Purity for Polysilicon Production

MG-Si at 98–99% purity cannot produce solar cells with commercial efficiency. The solar industry uses the Siemens process (developed by Siemens AG in the 1950s and still dominant today) to produce polysilicon at 9N purity.

The process has three steps:

1. Trichlorosilane synthesis: MG-Si reacts with hydrogen chloride (HCl) at 300°C to produce trichlorosilane (SiHCl₃), a volatile liquid: Si + 3HCl → SiHCl₃ + H₂
2. Fractional distillation: Trichlorosilane is distilled multiple times to separate it from boron, phosphorus, and other dopant impurities, which would create uncontrolled p-n junctions.
3. Chemical vapor deposition (CVD): Purified trichlorosilane decomposes on heated silicon rods at 1,100°C, depositing ultra-pure silicon: SiHCl₃ + H₂ → Si + 3HCl

The result is polysilicon — shiny, brittle chunks of ultra-pure silicon that look like metallic glass. These chunks are the raw material for both monocrystalline and multicrystalline wafer production. The Siemens process accounts for roughly 80% of global polysilicon production. The main alternative, the fluidized bed reactor (FBR) process used by REC Silicon, produces granular polysilicon at lower energy cost but slightly lower purity.

Stage 3: Crystal Growth — The Fork Between Monocrystalline and Multicrystalline

This is the most consequential decision point in module manufacturing, and it determines efficiency, cost, and which degradation mechanisms apply. Two processes compete:

The Czochralski Method (Monocrystalline)

A single-crystal silicon seed is lowered into a crucible of molten polysilicon at 1,412°C (silicon’s melting point) doped with boron to create a p-type base. The seed is rotated slowly and pulled upward at a precisely controlled rate, causing silicon atoms to solidify onto the seed in perfect crystallographic alignment. After 20–40 hours, the result is a monocrystalline silicon ingot—a single, uninterrupted crystal structure 200–300 mm in diameter and 1–2 meters tall, weighing 150–300 kg.

Every atom in this ingot is aligned in the same crystal direction. There are no grain boundaries. Electrons travel long distances without encountering a recombination site, which is why monocrystalline cells achieve 22–24% efficiency in production. The Czochralski process is energy-intensive—roughly 80–120 kWh per kg of silicon—and slow, but the efficiency premium justifies the cost at current module pricing.

Directional Solidification (Multicrystalline / Polycrystalline)

Molten polysilicon is poured into a square mold and cooled from the bottom up, causing silicon to solidify into multiple crystal grains growing in different directions. The result is a multicrystalline block with visible grain boundaries—the characteristic blue-mosaic pattern of older panels.

Directional solidification is faster and cheaper than Czochralski, but the grain boundaries become recombination highways where electrons lose energy instead of reaching the external circuit. Multicrystalline cells typically achieve 17–19% efficiency. According to the International Technology Roadmap for Photovoltaics (ITRPV) 2025 edition, multicrystalline silicon fell below 10% of global wafer production in 2024, as monocrystalline TOPCon economics displaced it in virtually all market segments.

Stage 4: Wafer Slicing — Diamond Wire Saws and Kerf Loss

The cylindrical monocrystalline ingot is first “squared off” by cutting the curved sides to produce a pseudo-square cross-section that fits more tightly into rectangular module frames. The ingot is then sliced into wafers using a multi-wire saw strung with diamond-coated wire, moving at high speed through a bath of cutting fluid.

Modern wafers are 180 µm thick—compared to 350 µm in 2005. Thinner wafers use less silicon per cell (silicon is the most expensive raw material in a module), but they are more fragile and require tighter handling protocols. The kerf loss—silicon that becomes sawdust during cutting—currently averages 70–80 µm per cut, meaning roughly 30–40% of the ingot mass is lost to cutting. Reducing kerf loss is a major ongoing cost-reduction focus in the industry.

After slicing, wafers undergo inspection for microcracks, bow (warping), and thickness uniformity. Cracked wafers cause cell micro-fractures that appear invisible on visual inspection but degrade performance progressively under thermal cycling—the same failure mode identified by electroluminescence (EL) imaging during incoming inspection at the factory or during annual O&M.

Stage 5: Wafer Processing — Doping, Texturing, and the p-n Junction

A raw silicon wafer is electrically inert. Turning it into a solar cell requires creating a p-n junction—the fundamental architecture that generates voltage from photons.

Boron doping (p-type base): For PERC cells, the wafer already contains boron from the Czochralski melt, creating the p-type bulk. For N-type TOPCon cells, the base is phosphorus-doped (n-type) from the Czochralski melt.

Texturing: Wafers are etched in sodium hydroxide solution to create microscopic pyramidal surface structures 1–5 µm tall. This random pyramid texture increases the optical path length of incoming photons by approximately 40%, reducing surface reflection from 35% (polished silicon) to under 10%. Texturing is one of the most cost-effective efficiency improvements in the entire manufacturing chain.

Phosphorus diffusion (for PERC) or tunnel oxide / polysilicon deposition (for TOPCon): In PERC cells, wafers are exposed to phosphorus oxychloride (POCl₃) gas at 850°C, which diffuses phosphorus into the front surface to create the n-type emitter. In TOPCon cells, an ultra-thin tunnel oxide (1–2 nm of SiO₂) plus a heavily doped polysilicon layer is deposited on the rear—this “passivated contact” dramatically reduces recombination losses and is the key innovation that pushes TOPCon efficiency above 23%.

Stage 6: Anti-Reflective Coating and Passivation Layers

Even after texturing, silicon still reflects some incoming light. A silicon nitride (SiNx) anti-reflective coating deposited by plasma-enhanced chemical vapor deposition (PECVD) at 400°C serves two functions:

1. Optical: Its refractive index (typically 2.0–2.1) is optimized to minimize reflection at the peak solar spectrum wavelength (600 nm). Combined with texturing, overall reflection drops below 3%.
2. Passivation: SiNx passivates dangling silicon bonds at the cell surface, reducing surface recombination velocity and increasing open-circuit voltage (Voc) by 15–25 mV.

For TOPCon cells, additional passivation layers of aluminum oxide (Al₂O₃) are deposited on the rear surface by atomic layer deposition (ALD). Al₂O₃ provides field-effect passivation—negative fixed charges that repel minority carrier electrons from the rear surface, further reducing recombination.

These passivation stack choices—SiNx thickness, Al₂O₃ layer quality, tunnel oxide integrity—are the primary sources of performance variation between nominally identical module models from different manufacturers. This is why ALMM certification and third-party quality audits (IEC 61215 / IEC 61730 certification, flash test data, EL imaging from production lots) are non-negotiable for bankable projects under MNRE guidelines.

Stage 7: Metal Contact Screen Printing and Firing

Solar cells generate electron-hole pairs under illumination, but those electrons need a low-resistance path to flow to an external circuit. Metal contacts provide that path.

Screen printing is the industry-standard process: silver paste is pushed through a patterned screen (like a stencil) onto the front and rear of the cell, then dried. The pattern creates thin “fingers” (the fine lines visible on a solar cell) connected to wider “busbars.” More fingers reduce the distance electrons travel laterally (lower series resistance) but block more light; fewer fingers transmit more light but increase series resistance. Modern half-cut cells use up to 5–6 busbars, and multi-busbar (MBB) designs with 9–12 busbars further reduce internal resistance losses.

After printing, cells go through a firing furnace at 800–900°C for 2–3 seconds. This rapid thermal process burns through the SiNx anti-reflective coating where the silver fingers are printed, creating an ohmic contact directly to the silicon. Firing temperature and duration are tightly controlled: over-firing destroys the passivation layer and shunts the junction; under-firing leaves high-contact resistance.

The silver content in screen-printed cells is a significant cost driver—silver paste accounts for roughly 10–15% of total module manufacturing cost at current prices. The industry is actively transitioning to copper-based contacts (which are cheaper but harder to process without oxidation) and silver-copper alloys.

Stage 8: Cell-to-Module Assembly — Stringing, Lamination, and Framing

Individual solar cells produce 0.5–0.7 V at roughly 10 A. A standard 580 Wp module contains 144 half-cut cells connected in two groups of 72 series cells (the half-cut architecture splits each cell, halving current and reducing resistive losses). The assembly process:

1. Tabbing and stringing: Copper interconnect ribbons (tabs) are soldered to cell busbars using automated tabbing machines. Cells are then connected in series strings using a stringer machine. String alignment tolerances are measured in tenths of a millimeter; misalignment causes mechanical stress during thermal cycling, increasing microcrack risk.

2. Layup: Strings are laid on a sheet of tempered low-iron solar glass (3.2 mm typical), then covered with EVA (ethylene-vinyl acetate) encapsulant film, then another EVA layer, then the backsheet (typically a white or clear polymer film, or for bifacial modules, a second glass sheet).

3. Lamination: The layup goes into a laminator press at 140–150°C under vacuum for 15–20 minutes. EVA melts, flows around the cells, and cross-links into a semi-rigid, UV-resistant matrix that bonds glass, cells, and backsheet into a single unit.

4. Framing: An anodized aluminum frame is bonded to the laminate’s perimeter with silicone adhesive. The frame provides mechanical rigidity for mounting and protects the module edge.

5. Junction box installation: A weatherproof junction box containing bypass diodes is bonded to the rear of the module and connected to the positive and negative output cables.

Stage 9: Quality Testing — What Flash Tests, EL Imaging, and Flash IV Curves Measure

A module leaving the lamination press cannot be sold without passing a battery of quality and performance tests. These tests are the manufacturing-side counterpart to the field-side inspection protocols EPCs run during commissioning.

Test	What It Measures	Failure Threshold
Flash test (STC I-V curve)	Peak power, Voc, Isc, fill factor at standard test conditions	Power below rated Wp -0% / +5%
Electroluminescence (EL) imaging	Inactive cell areas, microcracks, broken fingers, dead cells	Any dark area exceeding 3–5% of cell area
Thermal imaging (IR)	Hot spots indicating shunted cells, broken contacts, or bypass diode faults	Hot spots > 10°C above average cell temp
Insulation resistance	Leakage between cell circuit and frame (PID risk proxy)	< 50 MΩ at 500 V DC
Wet leakage current	Moisture ingress through frame seal or backsheet	> 50 µA indicates seal failure
Visual inspection	Scratches, bubbles, delamination, cell cracks	Any laminate bubble > 5 cm² or edge delamination

According to IEC 61215-2:2021 Photovoltaic Modules — Design Qualification and Type Approval, modules must pass damp-heat (85°C / 85% RH for 1,000 hours), thermal cycling (200 cycles, -40°C to +85°C), and UV pre-conditioning before type approval. These tests are conducted on samples; manufacturers use inline flash testing and statistical EL imaging on production lots to verify consistency.

The Sand-to-System Quality Ladder (SSQL) Framework

The SSQL Framework maps each of the nine manufacturing stages to the quality decision an EPC should care about when specifying modules:

Monocrystalline vs Multicrystalline vs TOPCon: The EPC Decision Matrix

Dimension	Multicrystalline PERC	Monocrystalline PERC	Monocrystalline TOPCon
Crystal structure	Multiple grains	Single crystal	Single crystal
Module efficiency (production)	17–19%	20–22%	22–23.5%
LID susceptibility	Moderate (P-type)	Moderate (P-type)	None (N-type)
Temperature coefficient (Pmax)	-0.40%/°C	-0.38%/°C	-0.29 to -0.32%/°C
ALMM listed in India	Limited	Yes	Yes (major manufacturers)
Cost relative to Mono PERC	-5–10%	Baseline	+8–15%
Bifacial option	Rarely	Yes	Yes (primary market format)
Best deployment	Lowest-cost constraint	General C&I rooftop	Utility scale, high-irradiance

Verdict. Multicrystalline modules have been displaced from virtually all new Indian project BOQs by mid-2025. Monocrystalline PERC remains appropriate for budget-constrained rooftop C&I projects below 1 MW. N-type TOPCon is the correct specification for any SECI tender, IREDA-financed ground-mount, or high-ambient-temperature site—the lower temperature coefficient alone recovers 1.5–2% of generation in locations where panels regularly exceed 55°C. For detailed module specification guidance aligned to your project’s engineering requirements, contact Heaven Designs.

How Heaven Designs Helps with Module Specification and BOQ Engineering

Every project BOQ Heaven Designs produces includes module specification language that traces directly back to manufacturing quality checkpoints—crystal type, LID testing protocol, EL sampling requirement, and ALMM / BIS certification status. This is not boilerplate: it is a procurement gate document that protects your lender acceptance and DISCOM interconnection timeline.

• Solar Rooftop Detailed Engineering Design — complete IFC-grade BOQ with module acceptance criteria, LID protocol notes, and PVsyst degradation factor selection. Supports DISCOM net-meter application in all major states.
• Solar Ground Mount Design — utility-scale layout with ALMM-compliant module specification, bifacial gain modeling, and bankable PVsyst P50/P90 yield for IREDA or PFC financing.
• Solar Permit Design (USA) — NEC 2023-compliant SLD, GA, and structural drawings with module spec that satisfies AHJ requirements across 38 states. Includes CEC/UL listing verification.
• STAAD Pro Reports — structural verification for rooftop or ground-mount mounting systems sized to the specified module’s wind and snow load parameters per IS 875 Part 3.
• Download sample deliverables — see how a real BOQ and SLD look for a rooftop or ground-mount project.

FAQ

What type of sand is used to make solar panels?

Solar panels do not use ordinary beach or construction sand. They require high-purity quartz rock (SiO₂ purity >99.5%) sourced from specific geological deposits in Brazil, Norway, and parts of India. Beach sand contains iron, aluminum, and other metallic impurities at parts-per-million concentrations that are acceptable for construction but catastrophically performance-damaging in a solar cell. The quartz is crushed and processed through carbothermic reduction and Siemens-process purification to achieve the 9N (99.9999999%) purity required for solar cells.

What is the difference between monocrystalline and multicrystalline solar panels?

Monocrystalline panels use silicon wafers cut from a single crystal ingot grown by the Czochralski process, producing a uniform crystal structure with no grain boundaries—giving 22–24% production efficiency. Multicrystalline panels use wafers cut from blocks solidified from multiple crystal grains, producing visible grain boundaries that increase electron recombination and limit efficiency to 17–19%. Multicrystalline panels are cheaper to manufacture but have been largely displaced in commercial markets by the efficiency advantage of monocrystalline TOPCon at comparable pricing.

Why are solar panels getting more efficient over time?

Panel efficiency improvements come from several parallel engineering advances: the transition from P-type PERC to N-type TOPCon (passivated contact architecture that reduces rear-surface recombination), the adoption of half-cut cells (which halve internal current, reducing I²R losses), multi-busbar designs (which shorten electron collection paths), larger wafer formats (M10 and G12, reducing the frame-to-cell area ratio), and improved anti-reflective coating and texturing processes. According to the ITRPV 2025 Roadmap, average commercial module efficiency is projected to reach 24% for monocrystalline products by 2027.

How long does it take to manufacture a solar panel?

The total elapsed time from polysilicon production to a finished, tested module is approximately 3–5 days on a continuous production line, broken down roughly as: polysilicon production (batch process, 72–96 hours), ingot growth (20–40 hours per ingot), wafer slicing and cleaning (4–8 hours), cell processing including diffusion, PECVD, and screen printing (8–12 hours), module assembly and lamination (4–6 hours), and final testing (1–2 hours). At a 1 GW annual-capacity factory, this equates to roughly 2,700 MW of modules produced per day if all lines run at full utilization.

What is the ALMM and why does it matter for solar panel procurement in India?

The ALMM (Approved List of Models and Manufacturers) is maintained by MNRE and lists solar PV modules that have been verified for domestic manufacturing traceability, BIS certification compliance, and declared manufacturing capacity. Only ALMM-listed modules can be used in projects receiving central government financial support—including PM Surya Ghar subsidies, SECI tenders, and ISTS-waiver projects. Procuring non-ALMM modules for these projects creates a compliance risk that can block CFA disbursement or DISCOM interconnection approval. For the current ALMM list and its implications for your BOQ, see our guide on ALMM compliance.

What happens to solar panels at end of life?

Solar module recycling is an emerging but not yet mature industry. The glass (approximately 75% of module mass) can be recycled through standard glass processing. The aluminum frame is recyclable at standard scrap values. The EVA encapsulant and backsheet require thermal or chemical delamination, which is energy-intensive. Silicon in the cells can be reclaimed but typically at lower purity than solar-grade silicon. The IRENA / IEA-PVPS End-of-Life Management report estimates that by 2050, solar panel waste could reach 78 million tonnes globally, making recycling infrastructure a critical policy and engineering challenge for the solar industry.

How does the manufacturing process differ for bifacial panels?

Bifacial panels use a transparent rear surface (second glass sheet or transparent backsheet) instead of the standard white polymer backsheet. The cell architecture is identical to standard monofacial TOPCon or HJT, but the module assembly uses a double-glass lamination process. Double-glass modules are heavier (approximately 23–25 kg vs 18–20 kg for standard framed) but have lower moisture vapor transmission rates—which improves long-term stability in high-humidity coastal environments. The bifacial gain from rear-side irradiance ranges from 5% to 30% depending on ground albedo and mounting height, and must be modeled in PVsyst using the bifacial gain setting with verified albedo data from site measurements.