Solar Engineering P1 Reference 5 min read Reviewed July 8, 2026 Nirav Dhanani Nirav Dhanani

Voltage Drop

Voltage drop is the voltage lost along PV conductors due to resistance. Learn the formula, NEC guidance and common targets of 2% DC and 1% AC.

Quick answer

Voltage drop is the reduction in voltage along a conductor caused by its resistance and the current it carries. NEC informational notes suggest limiting branch circuits to 3% and feeders plus branch circuits to 5%; solar designers often target lower DC and AC drop to reduce energy losses and keep inverters within their operating range.

Quick Facts

FieldDetail
TermVoltage Drop
CategorySolar Engineering
Engineering DisciplineElectrical Design
NEC Reference215, Chapter 9 Table 8/9
Target≤ 2% DC, ≤ 1% AC
Difficulty LevelBeginner to Intermediate

Voltage Drop Formula

DC voltage drop

Vd = 2 × I × L × (R / 1000)

where:
- I = current (A)
- L = one-way length (ft)
- R = conductor resistance (Ω/1000 ft)
- factor 2 accounts for the round-trip (out and back)

Voltage drop percentage

Vd_% = (Vd / V_string) × 100

Worked example

String at Vmp = 600 V, Imp = 13.5 A. Run to inverter: 80 ft (one-way). 10 AWG copper, R = 1.0 Ω/kft.

Vd = 2 × 13.5 × 80 × 1.0 / 1000 = 2.16 V
Vd_% = 2.16 / 600 = 0.36% → ✓ excellent

AC voltage drop

AC circuits add a reactance term alongside resistance, so the DC formula above only tells part of the story once the run leaves the inverter:

Vd = I × (R × cos θ + X × sin θ)

where:
- R = conductor resistance (Ω/1000 ft)
- X = conductor reactance (Ω/1000 ft, from NEC Chapter 9 Table 9)
- θ = power factor angle

For solar inverters operating near unity power factor, cos θ ≈ 1 and the reactance term shrinks, so AC voltage drop tracks close to the DC calculation for the same conductor and length.

Longer inverter-to-panel or panel-to-transformer runs on three-phase feeders are where the reactance term starts to matter, this is the case where an AC cable sizing reference that carries Table 9 values, rather than a hand calc with Table 8 resistance only, earns its keep.

Resistance Values (Copper, NEC Chapter 9 Table 8)

AWG / kcmilΩ/kftSuitable for
142.52Short residential
121.59Residential DC
101.0DC home runs ≤100 ft
80.63DC home runs ≤200 ft
60.40Combiner outputs
40.25Sub-feeder
20.16Sub-feeder
1/00.099Feeder
4/00.049Feeder
250 kcmil0.0419Feeder
500 kcmil0.0214Sub-station

Aluminum is ~60% the conductivity of copper, adjust upsizing accordingly.

Design Targets

  • DC home run from combiner to inverter: ≤ 2%.
  • AC from inverter to main service: ≤ 1%.
  • AC sub-feeder to commercial inverter pad: ≤ 0.5%.

How to Reduce Voltage Drop

  1. Shorter wire runs: locate the combiner box near the inverter.
  2. Larger conductors: doubling size halves Vd; cross-check the selection against a DC cable sizing reference rather than rounding up by feel.
  3. Higher string voltage: 1,500 V plants have 1/4 the current of 750 V for same power, dropping voltage drop by 75%.
  4. Aluminum upsizing: economical for large feeders, requires 1 AWG up for equivalent ampacity.
  5. Multiple parallel runs: splitting current among multiple conductors.

Common Mistakes

  1. Forgetting the factor of 2 (round-trip) in DC voltage drop calculation.
  2. Using one-way length only for AC three-phase circuits where neutral/return doesn’t apply.
  3. Ignoring voltage drop when checking MPPT minimum.
  4. Designing AC drop within limits but DC drop over limits.
  5. Using cold-temperature resistance when hot operating conditions yield higher R.

Best Practices

  • Show voltage drop calculation on the SLD for DC and AC runs.
  • Use high-temperature resistance values (75°C - 90°C) for derated conditions.
  • Cross-check string Vmp at site hot temperature plus expected Vd vs. inverter MPPT_min.
  • Use voltage drop calculators (NREL Wire Sizer, Mike Holt, Bluebeam plugins).

Standards & Certifications

  • NEC 215 Informational Note No. 2, Voltage drop recommendation.
  • NEC Chapter 9 Table 8, Conductor resistance values.
  • NEC Chapter 9 Table 9, AC resistance and reactance (large feeders).

Key Takeaways

  • Voltage drop = 2 × I × L × R / 1000 for DC round-trip.
  • Solar industry targets: ≤ 2% DC, ≤ 1% AC; NEC recommendation is ≤ 3% branch.
  • Include Vd in MPPT lower bound checking for hot-day Vmp.
  • Reduce Vd by larger conductors, shorter runs, or higher string voltages.
  • Always show the Vd calc on the SLD or in the conductor schedule.

Voltage drop rarely gets modeled in isolation, it shows up as one of the ohmic-loss line items in a PVsyst or HOMER Pro loss diagram, so a designer chasing a bankable P50 number needs the wire schedule and the yield simulation to agree; the PV yield simulation software comparison and P50/P90/P99 yield report guide both walk through where wiring losses sit in that stack.

On the electrical-drawing side, a solar SLD software package that auto-generates NEC-compliant one-lines is the practical way to keep the voltage drop schedule attached to the conductor sizes it was calculated for, rather than living in a separate spreadsheet that drifts out of sync.

Since voltage drop and MPPT tracking range interact directly on hot-day Vmp, teams comparing tracking-algorithm behavior against wire losses may also find Qbits Energy’s MPPT algorithm entry a useful companion reference.

Disclosure: Qbits Energy is a Heaven Designs group company.

Frequently Asked Questions

3 commonly searched questions about Voltage Drop.

How do you calculate voltage drop in a solar circuit?
For a DC circuit, multiply current by the round-trip conductor length and the conductor's resistance per unit length, then divide by circuit voltage for a percentage. Designers use the resistance values for the conductor's operating temperature and adjust for three-phase AC circuits.
Is NEC voltage drop limit mandatory?
For most PV circuits it is not mandatory, because the 3% and 5% values appear in informational notes rather than enforceable code text. Some local authorities, utilities, or project specifications add their own limits, so designers check those documents.
How can voltage drop be reduced in a solar design?
Options include larger conductors, shorter routes, higher string voltages, placing inverters closer to the array, or using copper instead of aluminium. Designers balance the cost of bigger cable against the value of energy saved over the system's life.

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